Publication: Numerical investigation on effect of integrated circuit (ic) design during encapsulation rocess
| datacite.subject.fos | oecd::Engineering and technology::Materials engineering | |
| dc.contributor.author | Randy, Ooi Yong | |
| dc.date.accessioned | 2025-10-28T12:33:51Z | |
| dc.date.available | 2025-10-28T12:33:51Z | |
| dc.date.issued | 2025-08 | |
| dc.description.abstract | This study presents a numerical investigation on the influence of integrated circuit (IC) design parameters on the flow behavior of epoxy molding compound (EMC) during the encapsulation process using ANSYS Fluent. EMC was modelled as a non- Newtonian fluid using the Cross-rheology model, and the simulation results were validated through comparison with benchmark flow front data. Four key IC design parameters were evaluated: Through-Silicon Via (TSV) integration, microbump pitch (640–1120 μm), bump array configuration (perimeter, semi-full, full), and chip stacking levels (1–4 layers). The addition of TSVs reduced fill volume by 1.7% and significantly increased central pressure and localized viscosity, leading to greater void formation risks. Reducing microbump pitch improved filling uniformity but increased backpressure, with the 0.80 mm pitch yielding the lowest void volume (4.9%). Full arrays resulted in more complex flow paths and localized voids up to 5.1%, while perimeter arrays achieved the most uniform filling and lowest voids (4.2%). Increased chip stacking heightened structural complexity and pressure gradients. Single-chip designs exhibited central deformation, while four-stack configurations reduced maximum deformation, although uneven mid-layer stress concentrations were observed. The results demonstrate that IC geometry has a substantial effect on flow dynamics, pressure distribution, and structural reliability in encapsulated devices. The simulation framework developed provides a predictive, cost-effective tool for optimizing encapsulation design and minimizing failure risks in advanced 3D IC packaging. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/22987 | |
| dc.title | Numerical investigation on effect of integrated circuit (ic) design during encapsulation rocess | |
| dc.type | Resource Types::text::report::technical report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |