Publication:
Thermal resistance in multichip modulus

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Date
2002-03-01
Authors
Beh, Kok Seng
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All packages will ultimately fail. Almost half of the failures in electronic packages occur due to thermal problems. The resistance to the flow of electrical current through the leads, poly-silicon layers and transistors compromising a semiconductor device, results in significant internal heat generation within an operating microelectronic component. Successful thermal packaging relies on a judicious combination of materials and heat transfer mechanisms to stabilize the component temperature at an acceptable level. The minimization of thermally-induced failures often requires the reduction of the temperature rise above the ambient and temperature variation within the packaging structure. Within the package, heat conduction is the only mode of heat transfer that occurs. Therefore, thermal resistance within a given package needs to be determined to build up an effective thermal management of the package. For multichip modulus, the portion between two chips for a double chip package for example, remains as a critical part in thermal management that need to be study deeply. Also, both two-dimensional and three-dimensional effects exist within the package. As conduction shape factor has a direct relation to thermal resistance, this is the thing that needs to be taken into account in thermal problems. Therefore, it is essential to explore the feasibility of using conduction shape factors in evaluating the thermal resistance of an electronic package. First, this is being done in a two-dimensional way, and will eventually lead to the evaluation in a three-dimensional way which gives us a more accurate prediction and provide good agreement with the actual value. A package build up comprises of different shapes and each shape had its own shape factor. For a model, the effects of shape changing on conduction shape factor are analyzed. More models are created and analyzed in order to give a more general approach to the analysis being done. Comparison among models is done and analysis is being carried out for thermal distribution. By having a general solution for thermal resistance which developed based on the variation in conduction shape factor for multichip modulus, thermal resistance obtained could be used to predict the heat flow inside the package and derive the junction temperature of the given package with high accuracy.
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