SILICON n-CHANNEL METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR FABRICATION AND ITS EFFECT ON OUTPUT CHARACTERISTICS
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Date
2012-10
Authors
MOHD RASHID, MOHD MARZAINI
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Abstract
n-channel metal oxide semiconductor field effect transistor (n-MOSFET)
fabrication requires specialized and expensive technologies such as ion implantation,
chemical vapor deposition (CVD) and hazardous gases such as silane (SiH4), HCl
and hydrogen. Low cost emulsion photomask with 35 μm channel length is used in
this work. To reduce the device’s channel length, and not be dependent on the
dimensional limitation of the photomask, two methods are employed. One is by
overdeveloping of photoresist and fabricating a different MOSFET structure namely
the vertical MOSFET (VMOSFET) where channel length is defined by anisotropic
Si etching using tetramethylammonium hydroxide (TMAH) instead of lithography.
Required processes for fabrication which are Si etching, Si oxidation and phosphorus
doping by spin on dopant (SOD) technique were studied. Smooth etched Si surface
at 20 nm rms was obtained for TMAH concentration of 18 wt% having etch rate at
0.3 μm/min. In SOD phosphorus diffusion, 950°C diffusion temperature was used to
minimize p-n junction leakage. To emulate hydrogenation of Si-SiO2 interface,
dry/wet/dry gate oxidation follow by post Al metallization anneal at 450°C in N2
ambient was done. Higher oxide breakdown and better retention to oxide leakage
was observed for dry/wet/dry gate oxide compared to dry gate oxide. For a self
aligned oxide doping mask on VMOSFET Si (111) sidewall, oxidation at lower
temperature 900°C achieved 30% thicker SiO2(111)/SiO2(100) compared to 12% at
higher temperature of 1000°C due to the crystal orientation-sensitive oxidation linear
rate constant dominating at lower temperature. A functioning 20 μm channel length
planar n-MOSFET has been fabricated having drive current of 13.8 μA/μm,
transconductance at 2.93 mS/mm and channel mobility at 217 cm
2
/V.sec. This
validates the feasibility of photoresist overdevelopment to reduce channel length so
that it is narrower than defined by the photomask. Obtained threshold voltage VT
was low at -4V suspected due to p-n junction reverse bias leakage, conduction paths
in Si substrate or due to surface channel leakage effects. No transistor action
occurred in VMOSFET output characteristics suspected due to phosphorus dopant
penetration through the oxide mask on its sidewall. Effects of gate oxide leakage and
high resistance on planar n-MOSFET’s output characteristics were observed and
explained where negative drain to source current (IDS) and slower IDS increase at low
drain to source voltages (VDS) occurred for the respective conditions.
Description
Keywords
METAL OXIDE , EFFECT TRANSISTOR