Influence of copper pillar bump structure on flip chip packaging during reflow soldering
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Date
2019-05
Authors
Chong, Jia Jun
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Abstract
Consumer electronics market is one of the fastest growing markets in the world. Flip chip (FC) technology is one of the technologies for interconnecting semiconductor devices, and with the demand for shrinking in footprint of electronic packages, FC technology must handle the increase in I/O interconnect density, and at the same time need to offer higher performance, more function, at lower cost. Furthermore, with the restriction of usage of leaded solder, industry needs a solution to overcome the hassle, and copper (Cu) pillar bump FC appears as a good solution. However, Cu pillar FC is not widely used nowadays because its reliability remained a concern. Thus, optimization of the technology must be done. In this work, computational fluid dynamic (CFD) approach is used to model the reflow soldering process of Cu pillar type FC, particularly in reflow stage. Volume of Fluid (VOF) modeling and Solidification/Melting modeling are used for this simulation purpose. A simulation model which capable to visualize the melting and solidification of solder is presented in this work. The effect of diameter of Cu pillar on reflow soldering is investigated. Findings suggest that the solder volume is the key factor affecting reflow soldering. However, findings also hinted that the capability of the numerical model is limited due to inability to capture displacement of solid during simulation. Future recommendation is suggested to overcome the limitation.