Development Of Efficient Multi-Level Discrete Wavelet Transform Hardware Architecture For Image Compression
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Date
2015-07
Authors
HASAN AL-JUMAIL, KHAMEES KHALAF
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Abstract
Focusing on the intensive computations involved in the discrete wavelet transform (DWT), the design of efficient hardware architectures for a fast computation of the transform has become imperative, especially for real-time applications. With this overall objective, the mapping of the computational tasks associated with the various resolution levels of the 5/3 DWT is first mathematically modeled, and then a modified computation of the DWT stages are explored from the standpoint of evading computing high frequency subbands. Furthermore, a Haar wavelet transform (HWT) is used for comparison. The proposed forward DWT (FDWT) and its inverse DWT (IDWT) hardware architecture filter generated similar results compared to the MATLAB model for the seven levels of DWT decomposition. Simulations were performed using grayscale images of different sizes to validate the proposed design and attain speed performance appropriate for a number of real-time applications. Four versions of the design are developed in this study, 64×64, 128×128, 256×256, and 512× 512 pixels image sizes. FDWT circuit of the proposed 5/3 2-D DWT architecture can process a 256×256 image in 2.07301 ms, which is at least four times faster than that of the other JPEG2000 and HWT FPGA implementation with less hardware utilization. The proposed 5/3 FDWT filter produced 127 slices of hardware logic and register element area, which comprises less than 1% of the Altera DE2 development board Cyclone II FPGA hardware area.
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Keywords
Development Of Efficient Multi-Level Discrete Wavelet , Transform Hardware Architecture For Image Compression