Method Of Assembly On Wafer Level Chip Scale Package
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Date
2007-09
Authors
Gooi, Boon Huan
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Abstract
In electronic packaging. cost reduction for assembly packaging is an on going
activities as electroinc package selling price is depreciated over the year. To make good
profit out from the selling price. cost of the assembly has to be reduced accordingly. In
this thesis. a cost reduction evaluation is carried out on the Land Grind Array package.
Fairchild micro molded lead less (I-I-MLP) package is a Land Grid Array package using
Bismalemide Triazine (BT) as a base to construct the package with footprint dimension
1.45mm (Length) x1.00mm (Width) xO.55mm.
There are few options to reduce the package cost to make it competitive in the
market. One of the method is to use lower materials cost to assemble the package. This
project summarize work being done on how to reduce package cost by replacing BT
substrate with copper leadframe.
A prototype samples has been assembled with copper leadframe. A
major issue is the die size which is too small. The small die size not able to attach onto
the copper leadframe (using chip on lead concept) is resolved by introducing a bare
silicon clip into the process flow. A bare silicon clip is attached onto the copper
leadframe to act as a die attach pad. This allows the die attached on to the silicon clip.
Reliability results show that there are no package quality issues when the BT substrate
is substituted by the copper leadframe. Most important. a great savings about 45% of the
package materials cost is achieved from the raw material when BT substrate is
substituted by the copper leadframe.
Description
Keywords
A cost reduction evaluation is carried out , on the Land Grind Array package