Design Of 10 Ghz Negative Resistance Dielectric Resonator Oscillator
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Date
2015-01
Authors
MOHAMMAD ZAKI, SYAZANA BASYIRAH
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Abstract
The wireless communication market has been experiencing tremendous growth and since the number of wireless subscribers and the amount of RF interference continue to increase, modern communication standards demand excellent phase noise performance from local oscillators in transceivers. Noise is one of major concern in oscillators because even a small amount of noise in an oscillator leads to dramatic changes in its frequency spectrum and timing properties. In general, an oscillator‟s phase noise determines the overall communication system‟s capability. The design of low phase noise oscillators faces many challenges at microwave and millimeter-wave frequencies. The main limiting factor in designing low phase noise oscillators at these frequencies is the low quality factor of resonators due to high conductor and dielectric losses. Therefore, in current microwave and millimeter-wave systems, DROs are widely employed. This dissertation emphasized on the effect of using dual transistors towards the oscillation frequency, output power and phase noise in the design of negative resistance DRO at 10 GHz. The DRO consists of E2000 series material disc type resonator with a diameter of 5.1 mm from Temex Ceramics, ATF-36077 GaAs pHEMT from Agilent and the Rogers RO4003C PCB with dielectric constant of 3.38 and 0.813 mm thickness. The uniqueness of this work compared to others was the dual transistors negative resistance DRO was designed in ADS with the help of WPD techniqueto divide and combine two sub-oscillators in order to achieve higher output power and low phase noise. Since a phase noise exhibited by a 10 GHz DRO in the current market is between -110 dBc/Hz and -120 dBc/Hz, a metal housing was implemented to reduce any possible of noises by preventing the output power from being lost in the radiated fields. The DR simulation result by using CST MWS produced a resonant frequency of 11.255 GHz and generating an insertion loss of 1.1918 dB. The simulation result for dual transistors negative resistance DRO schematic circuit in ADS produced an oscillation frequency of
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10.61GHz at output power of-58.698 dBm and a phase noise of-103.440 dBc/Hz. The measurement result exhibited an oscillation frequency of 11.79805 GHz at output power of -1.8 dBm and a phase noise of-81.03 dBc/Hz. The implementation of dual transistors negative resistance DRO was provento enhance the output power and lower the phase noise compared to single transistor negative resistance DRO. Therefore, the dual transistors negative resistance DRO hardware was successfully produced with lower phase noise and higher output power at an oscillation frequency approximately 10 GHz.
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Keywords
Design Of 10 Ghz Negative Resistance , Dielectric Resonator Oscillator