Simulation Of Short Channel Vertical Mosfet Structures
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Date
2010-12
Authors
Ooi, Poh Kok
Journal Title
Journal ISSN
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Publisher
Universiti Sains Malaysia
Abstract
Recently, the end of the planar bulk complementary metal oxide semiconductor (CMOS) had become visible. Vertical metal oxide semiconductor field effect transistor (VMOST) structures are one of the promising structures for future CMOS technologies. There are still a lot of research needs to be done on the VMOST structures to mature as that of planar CMOS technologies. It is well known that there are many parameters needed to be considered in designing MOSFET. With the aid of computer-aided design, we can optimize the MOSFET parameters faster and with lower cost. This project is based on two-dimension (2D) simulation works. Simulators used are ATHENA, DEVEDIT and ATLAS from SILVACO International. ATENA and DEVEDIT are used to simulate the device structures. Meanwhile, ATLAS is used to predict the electrical outputs of the proposed parameters device structures with insight into the internal physical mechanisms associated with device operation. The aim of this project is to study NVMOST structures, which are VMOST growth with epitaxial layers (VMOST-EL), vertical MOSFET incorporating dielectric pocket (DP) (DP-VMOST) and vertical replacement gate (VRG) MOSFET. For VMOST-EL, the effects of various channel doping concentration, NC, on 80 and 50 nm channel length are discussed. VMOST-EL with L of 50 nm and NC of 2 x 1018 cm-3, has the Vth, JD and Joff of 0.22 V, 1227 μA/μm and 2.8 x 10-7 A/μm, respectively. The results revealed that NC have significant influence on electrical behaviours. Besides, for DP-VMOST structures, the effects of spacing between the pocket and the gate oxide, WC, on various NC are examined. DP-VMOST with WC = 10 nm and NC = 2 x 1018 cm-3 has JD of 1024 μA/μm, Joff of 2.2 x 10-8 A/μm and Vth of 0.32 V. The DP strongly decreases the depletion from drain to the channel as well as the p-n junction area which contribute to better short channel performance sub-100 nm VMOST. Additionally, there is a possibility to control the device output by only vary the WC rather than controlling the doping concentration or gate oxide thickness. As we compared to Donaghy et al. (2004) work, the trends are different for Joff, at a channel doping concentration of 3 x 1018 cm-3, the value of Joff obtained is lower than NC of 4 x 1018 cm-3. This phenomenon may due to the models used for characterization. Finally, for VRG-MOSFET, the effects of the width of the body region between the two channels, WB, with various NC are also investigated. It showed that body potential is strongly affected by the low WB and NC, which will cause the body region to become partial depleted or fully depleted. For VRG MOSFET with L = 50 nm, NC = 3.5 x 1018 cm-3 and WB = 200 nm, it shows Vth of 0.53 V, JD of 482.6 μA/μm and Joff of 3.31 x 10-13 A/μm. In contrast, work by Hergenrother et al. (1999) with L of 50 nm and NC of 3.5 x 1018 cm-3 showed Vth of 0.73 V, Joff of 5 x 10-10 A/μm and JD of 68 μA/μm. The disagreements exist because the simulation in this work is only available in 2-D VRG MOSFET structures. However, the structure introduced by Hergenrother et al. (1999) is “rectangular” surround structure with the width of 16.4 μm.
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Keywords
Vertical metal oxide semiconductor field effect transistor , one of the promising structures for future CMOS technologies