Publication: Formulation, implementation and analysis of the locally implicit voltage-in-current latency insertion method
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Tham, Zhi Kean | |
| dc.date.accessioned | 2025-05-07T07:12:51Z | |
| dc.date.available | 2025-05-07T07:12:51Z | |
| dc.date.issued | 2023-07 | |
| dc.description.abstract | Latency Insertion Method (LIM) is a speed up of transient simulation of large networks. As the name tells, this method introduces reactive latency in all branches and nodes of an arbitrary circuit to generate update algorithms for the voltage and current quantities over time. As the basic LIM algorithm has limitation on maximum simulation time step, it can be overcome with Voltage in Current Latency Insertion Method (VINC LIM) formulations, even with different nonlinearities considered. Due to its inaccuracy over higher time steps simulations of branch capacitor, a newly introduced locally implicit Voltage in Current Latency Insertion Method (LI VINC LIM) is proposed. This method aims to inherit the unconditionally stable criteria in VINC LIM algorithm and the accurate computation of fully implicit LIM methods on selected group of nodes. This method first selects the desired nodes of interest as a group of nodes and simulate the whole circuit with VINC LIM algorithm to obtain a precalculated result. These pre-calculated results will then be used as the input of the locally implicit matrix solver that solve the selected group of nodes implicitly. This new method is tested with circuits consisting linear and non-linear resistors and capacitors. It is found that this method only shows improvement in accuracy for circuit with linear and non-linear resistors up to 22.13 but does not show any changes on circuit with linear and non-linear capacitor (with most accuracy improvement within a range of 0.9-1.3). | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/21527 | |
| dc.language.iso | en | |
| dc.title | Formulation, implementation and analysis of the locally implicit voltage-in-current latency insertion method | |
| dc.type | Resource Types::text::report::technical report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |