Publication: Design and analysis of a low noise CMOS 180nm differential amplifier for sensing applications
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Date
2024-08
Authors
Ngo, Jia Yuh
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Abstract
Nowadays, sensors are widely used in many electronic devices due to its ability to automate certain task which can be produce a more precise result compared to
human control. The objective of this project is to design an operational transconductance amplifier (OTA) with the desired specification determined. Besides
that, the layout designed are required to pass DRC and LVS validation and area lesser than 1๐๐2. The last objective of this project is to conduct a post layout simulation to ensure that the performance deviation between layout and schematic is less than 10%. To achieve the objectives, the balance needs to be achieved between the critical parameters such as gain, gain bandwidth, slew rate and noise. Cadence Virtuoso tools is used to design the schematic and layout while using the full custom design approach when designing the layout. The results shows that the pre-layout simulation of the OTA provide the gain of 41.00 dB, slew rate of 34.4028 ๐ ยต๐ 30.33 MHz, noise of 23.4957 ยต๐ โ๐ป๐ง , unity gain bandwidth of and output voltage swing of 1.1351 V. For post layout simulation, the performance of OTA gives gain of 41.11 dB, unity gain bandwidth of 30.20MHz, slew rate of 34.3856 ๐ ยต๐ , noise of 20.1913 ยต๐ โ๐ป๐ง and output voltage swing of 1.1280 V. In conclusion, most of the objectives in this project has been achieved. The results obtained had met the design specifications. The layout designed had passed the DRC and LVS validation. Besides that, the layout area is 0.7924mm2 which is lower than the maximum chip size. The last objective of this
project which is the performance deviation between layout and schematic are less than 10% is partially achieved.