Publication:
VLSI Implementation Of A Systolic Array Viterbi Decoder

Simple item page
dc.contributor.authorMohd. Noh, Norlaili
dc.date.accessioned2025-11-18T06:31:18Z
dc.date.available2025-11-18T06:31:18Z
dc.date.issued1995-03
dc.description.abstractThis project is on developing a Vi terbi decoder which uses the trace-back method structured in a systolic array fashion. It is believed that this architecture can reduce the size of the decoder as it minimizes the connections between component modules and requires a smaller storage space. The trace-back method can reduce the amount of hardware which is normally a problem with register exchange decoder. It is also suitable for achieving a higher speed of operation as tracking, updating and storage of the information sequence can be accomplished simultaneously during a single clock cycle.
dc.identifier.urihttps://erepo.usm.my/handle/123456789/23107
dc.language.isoen
dc.subjectData transmission systems
dc.subjectDecoders (Electronics)
dc.titleVLSI Implementation Of A Systolic Array Viterbi Decoder
dc.typeResource Types::text::thesis::master thesis
dspace.entity.typePublication
oairecerif.author.affiliationUniversiti Sains Malaysia
Files
Collections
Pusat Pengajian Pendidikan Jarak Jauh