Publication: HBM3 VIP with protocol checks - synthesizable
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Wong, Ngei Hong | |
| dc.date.accessioned | 2025-05-07T07:58:37Z | |
| dc.date.available | 2025-05-07T07:58:37Z | |
| dc.date.issued | 2023-07 | |
| dc.description.abstract | The increasing complexity of digital systems introduces the likelihood of flaws and errors. Consequently, the importance of verification intellectual property (VIP) cannot be overstated, as it accounts for approximately 70% of the verification process compared to IP design. This study aims to develop a High Bandwidth Memory 3 (HBM3) Dynamic Random Memory (DRAM) transactor (VIP) on Xilinx Field Programmable Gate Array (FPGA), where the HBM3 DRAM transactor (VIP) serves as a model replicating the behaviour of the HBM3 DRAM. The focus of this research is to verify the read and write operations of the HBM3 DRAM through simulation using Vivado Simulator. Additionally, this research also aims to enhance the efficiency of validation by utilizing FPGA prototyping emulation. The simulation results demonstrate the successful development of the HBM3 DRAM VIP, as they conform to the specifications of the JEDEC Standard. Furthermore, the FPGA prototyping emulation exhibits a remarkable x5800 speedup compared to simulation, resulting in significantly accelerated validation. Overall, this research contributes to the advancement of HBM3 DRAM verification and provides valuable insights into the performance of FPGA prototyping emulation for efficient validation. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/21528 | |
| dc.language.iso | en | |
| dc.title | HBM3 VIP with protocol checks - synthesizable | |
| dc.type | Resource Types::text::report::technical report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |