Publication: Performance analysis and verification of energy efficient multiplier
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Date
2023-08
Authors
Lim, Ying Tong
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Abstract
Multipliers are the fundamental building block in Digital Signal Processing (DSP). Computation-Intensive Arithmetic Functions (CIAF) such as Multiply and Accumulate (MAC) which is multiplication-based operations are widely used in various DSP applications such as Fast Fourier Transform (FFT), filtering, convolution, arithmetic logic unit (ALU) and microprocessors. Multiplication dominated the execution time of the majority of DSP algorithms and the instruction cycle time of a DSP chip. In addition, performance, power consumption, and area are three crucial parameters in the very large scale integrated (VLSI) system design. In this project, a comparative analysis of Array Multiplier, Wallace Tree Multiplier, and Booth Multiplier by different criteria such as time delay, power and area were conducted. Architecture of these multipliers were designed using Verilog Hardware Description Language (HDL) while the simulation and synthesis were completed using Synopsys Electronic Design Automation (EDA) tools. The final post-layout results analysis has proven that the Booth Multiplier reduced the total power consumption by 19.24% (Array Multiplier) and 20.17% (Wallace Tree Multiplier). Moreover, the percentage of reduction of the critical path delay of Booth Multiplier are 28.40% (Array Multiplier) and 15.26% (Wallace Tree Multiplier). As the results, the Booth Multiplier is more power-efficient than the Array Multiplier and Wallace Tree Multiplier, while exhibiting significantly lower delay.