Publication: Enhancing soc design efficiency through supervised machine learning: a random forest approach for predicting timing exceptions
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Cheah, Zong Ken | |
| dc.date.accessioned | 2025-05-19T07:24:30Z | |
| dc.date.available | 2025-05-19T07:24:30Z | |
| dc.date.issued | 2024-08 | |
| dc.description.abstract | As System-on-Chip (SoC) design and manufacturing technology advance towards more intricate and complex designs, ensuring accurate timing analysis becomes increasingly challenging. Traditional methods require extensive manual efforts to construct and organize timing models across numerous process corners, leading to inefficiencies and potential errors. This study addresses the problem of automating the identification and classification of multi-cycle paths in SoC design, focusing on non-critical paths that influence overall timing performance. Leveraging machine learning, particularly a Random Forest algorithm, the proposed method aims to streamline this phase of the design process. The approach was evaluated against Logistic Regression and k-Nearest Neighbors (KNN) models using metrics such as F1 score, AUC ROC, and Precision-Recall AUC. The Random Forest model demonstrated superior performance, achieving a Precision-Recall AUC score of 95.33% and 99.89% in k-fold cross-validation, and identified multi-cycle paths with high precision and only 2 false negatives in a random sample of 100,000 datasets. Compared to conventional methods, this machine learning approach significantly reduces the time required for timing path review from days to hours and minimizes the need for extensive engineering resources. The findings highlight the potential for substantial cost savings and productivity improvements in SoC design verification, establishing a new standard for applying machine learning in this domain and paving the way for more innovative and efficient design processes in the future. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/21713 | |
| dc.language.iso | en | |
| dc.title | Enhancing soc design efficiency through supervised machine learning: a random forest approach for predicting timing exceptions | |
| dc.type | Resource Types::text::report::technical report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |