Publication: Design and analysis of cmos based rfic bandpass filter (bpf) for 1.9ghz range for cdma applications
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering | |
| dc.contributor.author | Ngoh, Say Kit | |
| dc.date.accessioned | 2024-07-18T07:44:55Z | |
| dc.date.available | 2024-07-18T07:44:55Z | |
| dc.date.issued | 2005-03-01 | |
| dc.description.abstract | The rapid development of wireless applications has created a demand for low-cost, compact, low-power hardware solutions. This demand has driven efforts to realize fully integrated, “single-chip” solution systems. While substantial progress had been made in the integration of many RF and baseband processing elements through the development of new technologies and refinements of existing technologies, progress in the area of fully integrated filters has been limited due to the losses (low Q) associated with integrated passive elements in standard IC process. The work in this report focuses on the design and analysis of CMOS based RFIC bandpass filter for center frequency of 1.90Hz. The entire design and analysis of the filter circuit have been carried out by ultilizing Cadence IC Design Tools (version 5.033). This report present a methodology for designing a Q-enhanced bandpass filter with active negative resistance generator circuitry to compensate for the filter losses due to the low quality factor of monolithic spiral inductors. The first phase of this work focus on the design and simulation of an ideal, fully integrated second order Butterworth bandpass filter (with -3dB bandwidth of 200MHz centered at 1.9GHz, corrensponding to the CDMA2000 Standard) ultilizing Cadence IC Design Tools with Silterra 0.18um Design Kit. The ideal bandpass filter which based on the paper work calculation is first constructed by using Silterra SMCMOS ideal component and the simulation results are observed. The ideal circuit is then simulated by using Silterra RF component (which include all parasitic effects) to show the actual filter performance. In the second phase of this work, a FET-based active negative resistance circuit is developed and being added into the bandpass filter circuitry to compensate the filter loss. With features of Cadence IC Design Tools, the filter is analyzed and optimized to obtain the best response. The best filter design achieves ≈ 0dB of passband gain or insertion loss while consuming 8.8mA of current from a ± 1.8V source (31.69mW). The filter provides more than 10dB of rejection at 1.5GHz and 2.5GHz. In the filter passband, the noise figure is 5.25dB and input return loss is -20dB. The filter response only suffered a minor frequency shift for a wide range of operating temperature. The bandpass filter has potential application as RF filters in CMOS integrated transceiver designs. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/19773 | |
| dc.language.iso | en | |
| dc.title | Design and analysis of cmos based rfic bandpass filter (bpf) for 1.9ghz range for cdma applications | |
| dc.type | Resource Types::text::report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |