Publication: Digital linear voltage regulator (DLVR) midrail custom layout
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Date
2024-08
Authors
Ooi, Ming Xuan
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Abstract
This study focuses on implementing a custom layout for the DLVR Midrail block, an analog-mixed signal circuit composed of active and passive components. The
layout is designed using Intel’s P1278 process node, which presents unique challenges due to its small feature sizes. The main objective is to minimize crosstalk and ensure reliability. The placement of standard cells and analog cells was separated to address these challenges. The analog layout design required specific routing techniques, including critical net shielding and robust routing. After the layout and routing, layout verification (LV) was conducted using in-house software and flow to ensure compliance with the foundry and stringent high voltage (HV) rules. Ansys Totem was used to test for reliability issues such as electromigration (EM) and self-heating (SH). This is crucial for verifying the block’s viability over its rated operating lifetime of ten years. Additionally, methods were explored for optimizing cell size, including overlapping instances and device clustering, with a target reduction of 5% to 10%. Yield and cost analyses were conducted to measure the potential cost savings from reducing the block size, considering various factors such as die size and wafer cost. Overall, this study presents an in-depth analysis of the challenges associated with implementing a custom layout for the DLVR Midrail block using Intel’s P1278 process nodes. The proposed design and testing methodologies provide a reliable, cost-effective solution for implementing complex analog-mixed signal circuit layouts.