Publication: Study and design for optimization of a current reuse low noise amplifier
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Date
2010-04-01
Authors
Tan, Kean Yeong
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Abstract
In this thesis, CMOS cascode LNA with Current Reuse Technique and inductive source degeneration structure was designed and analyzed. The Current Reuse Technique is not only able to meet the requirements of typical W-CDMA performance but also consume low power. The design was implemented on Silterra’s 0.18μm 6 metal-1 poly CMOS process. Current Reuse Technique was employed to reduce power consumption and achieve the same amplifier transconductance to enable the LNA to achieve good gain. Based on the measurement results obtained from the previous LNA design, some improvement had been done in the layout design which was able to produce better predicted performance of the current reuse LNA. The layout design use Cadence spectre RF and Calibre for post-layout simulation before the final tape-out. Post-layout simulation is very important as it takes into consideration the parasitic involved in the layout. It is used to verify the functionality of LNA circuits before final tape-out. In this project, distributed extraction of post-layout simulation was used since it provided more accurate and precise results. Besides, new bond pad was introduced in this work to replace the existing traditional bond pad. The new bond pad contributed approximately to 250fF of capacitances, which was almost half the traditional bond pad. The post-layout simulation using distributed extraction of the final designed LNA achieved noise figure of 2.392dB with forward gain (S21) of 17.44dB. It consumes 6.23mW with 3.461 mA current drawn from 1.8V supply voltage. Besides these, S11 and S22 are −14.48dB and −18.48dB respectively while reverse isolation (S12) is −51.40dB in a 50Ω environment. The Input Third-order Intercept point, IIP3 of the design is −2.70dBm.