Publication: Area optimization in active reference bandgap amplifier layout design
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Date
2023-07
Authors
Teh, You Han
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Abstract
In the general design flow of the Full Custom Integrated Circuit (IC), layout design was the backend of the design flow of an Integrated Circuit. Layout design was the geometric form of the schematic circuit and the layout design was transformed into a photolithographic mask layer during the fabrication process. In layout design, the unique needed of Datapath design were Area, Pitch-matched layout, and symmetry in an arrangement. Due to the high cost of materials, area optimization in layout design had become important to overcome challenges such as cost, complexity, and performance. The area of layout design reduced by area optimization to a compact size by following critical requirements and it could be started from the floor planning layout design step. The techniques of area optimization introduced in the project which includes the minimum distance rule, sharing diffusion region and guard ring, sharing well layer, and introduction of legging in the routing step. Euler’s Path also one of the theoretical techniques to determine the placement of the device to get the shortest routing distance. The project required to run physical verifications such as DRC, LVS, and Latch-up to check and ensure the layout design was clean with no errors. The layout design was designed by using Cadence Virtuoso Layout Suite XL and Schematic Editor tool was used to review the schematic circuit for routing and identify the sensitive blocks. Compared to the results with and without area optimization, the overall area layout was reduced by at least 20%, and eliminated the unwanted white space after implementing the area optimization techniques.