Publication: High speed phase-frequency detector with programmable output pulse width to avoid dead-zone
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Date
2024-08
Authors
Chan, Khar Mun
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Abstract
The utilization of phase locking, particularly in the form of phase-locked loops (PLLs), has been prevalent in electronics and communication systems since the early twentieth century. The focus of this final year project is on enhancing the phase frequency detector (PFD) component within PLLs, specifically through the
development of a high speed PFD with a programmable output pulse width to avoid dead-zones. Existing methods for PFD’s delay design face limitations, particularly concerning fixed and limited delay times, analog design instability, and complex control design, leading to compromised PLL performance. This research project addresses these issues by developing a programmable delay element for integration into the PFD's reset path, offering increased options for delay time through a simple digital control mechanism to enhance the flexibility and stability of the PFD. The project successfully designed and simulated a digital control variable delay element block with expanded delay options, incorporating enable control to avoid dead-zone occurrences in the PFD. A phase-frequency detector with programmable output pulse width is designed and simulated, with a process migration from lower technology nodes to 180nm, ensuring it functions well at a lower frequency of 70MHz. From the findings, it can be concluded that the developed programmable delay element offers a viable solution to the limitations in PFD design. Overall, the increased flexibility in delay adjustment using digital control contributes to improved PLL performance with simpler control, ensuring consistent and reliable operation across different manufacturing conditions.