Publication: Bottleneck simulation in mems manufacturing process
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering | |
| dc.contributor.author | Jamil, Azrul Haniedy | |
| dc.date.accessioned | 2024-01-31T08:11:45Z | |
| dc.date.available | 2024-01-31T08:11:45Z | |
| dc.date.issued | 2021-12-01 | |
| dc.description.abstract | The rate of increase of consumer demands and global competition between companies forced the industry to increase productivity by increasing the production capacity to meet the monthly throughput demand. The presence of a bottleneck is common theme faced by every industry that will reduce the throughput of a machine. Thus, to increase the throughput while at the same time reducing the impact bottleneck, one needs to look for the best model to accurately represent the production process. In this thesis, the utilization rate and machine capacity for the manufacturing system of different topologies simulation; that includes series and parallel framework, taken in consideration the bottleneck in the workstation being studied. By building the simulation model of the production line, the bottleneck process can be monitor and analyse in the simulation to use it to reduce the impact of bottleneck. Scheduling in the simulation model integrated in the model for the propose of obtaining the accuracy between simulated result and the actual production result with deviation differences below than 10% for controlling the bottleneck, thus, increasing machine utilization rate and meet the targeted results based on the capacity planning. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/18245 | |
| dc.language.iso | en | |
| dc.title | Bottleneck simulation in mems manufacturing process | |
| dc.type | Resource Types::text::thesis::master thesis | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |