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Study and analysis of the transistor size effects on the performance of silterra's 0.18 µm cmos inductively-degenerated cascode lna for w-cdma application

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Date
2009-04-01
Authors
Lim, Fang Rong
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This thesis presents an analysis of the transistor size effects on the performance of Silterra's 0.18 µm CMOS inductively-degenerated cascode low noise amplifier (LNA) for W-CDMA direct conversion receiver application. The size of the input transistor of the LNA was determined by using the power constrained method and the LNA was designed by using power-constraint simultaneous noise and input matching (PCSNIM) design technique. The theoretical analysis and the simulation results show that for the cascode LNAs, input transistor dominates the noise performance of the LNA while the cascode transistor contributes more to the linearity performance. The simulation result shows that the optimum size of input transistor and the cascode transistor to give the best noise and linearity performance are 300 𝜇m respectively. The noise figure is decreased about 0.8% and the linearity (IIP3) is increased about 4.13% after change the width of M1 and M2 to 300𝜇m. Noise figure does not change much when the width of cascode transistor is at least half of width of input transistor. As a conclusion, the input transistor and cascode transistor of the LNA can be designed to optimize the noise performance and linearity performance separately without trade offs.
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