Publication: Area optimization of phase lock loop (PLL), low-dropout (LDO) regulator and voltage-controlled oscillator (VCO) layout design in complementary metal-oxide semiconductor 40-nm technology
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Date
2023-08
Authors
Chai, Chern Hong
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Abstract
This research focuses on the area optimization of PLL (Phase-Locked Loop), LDO (Low Drop-Out) regulator, and VCO (Voltage-Controlled Oscillator) in the field
of physical design. The project addresses the need for improved layout optimization of PLL, LDO and VCO as the semiconductor chip size scales up to meet market demands. The objectives include applying various optimization techniques to get clean physical verification and achieve an area reduction of more than 35%. A range of optimization techniques are applied, such as grouping method, and sharing of source and drain, N-well, deep N-well, guard rings. The results and discussion section presents the findings of the floor-planning and optimization process. An optimized and a clean Design Rule Check (DRC) floor-planning is successfully obtained after meticulous effort. The total achieved area reduction percentage is 49.932%, as demonstrated by a bar chart highlighting the optimization process steps. In addition, physical verification such as Layout Versus Schematic (LVS), DRC, Latch-up check and antenna check are performed to ensure layout quality. The total achieved area reduction percentage is 49.932%, as demonstrated by a bar chart highlighting the optimization process steps. Based on the obtained results, it is concluded that all the objectives have been successfully achieved.