Publication: Design and characterization d flip-flop with synchronous and asynchronous preset and clock-enable
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Date
2024-07
Authors
Oh, Wei Sheng
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Abstract
Digital flip-flop plays a pivotal role in various applications within realm of digital electronics, serving as a vital element in memory units, sequential logic circuits and data storage systems. The performance of a digital flip-flop basically is referred to as propagation delay and power consumption. This project reports the timing characteristics and power consumption of a digital flip-flop with synchronous and asynchronous preset and clock-enable. The digital flip-flop used in this project is a modified transmission gate master-slave D flip-flop. The design consists of asynchronous control and synchronous control for the MSDFF. The design phase and analysis phase are completed by using Cadence Virtuoso® based on Silterra 180nm process technology node. A testing procedure will be carried out to determine the effect of the transistor configuration on the propagation delay and power consumption. After testing, the integrated circuit layout is drawn without any error on Design Rules Check (DRC), Layout Versus Schematic (LVS) and Parasitic Extraction (PEX). Post layout simulation is carried out to identify how the parasitic elements affect the performance of the flip-flop designed. This analysis gives everyone a deep understanding of the effect of transistor configurations affecting the performance of D flip-flop and the parasitic elements affecting the performance of D flip-flop. The results show that the propagation delay of the designed flip-flop varies with different operating conditions, with the lowest delay observed during asynchronous set operation at 104.044 ns and the highest during normal operation with CE_G set to HIGH at 249.873 ns. Power consumption during normal operation with CE_G set to HIGH at 337.9 µW. The post-layout simulations indicate a reduction in power consumption compared to pre-layout simulations due to the consideration of parasitic elements, which lower the effective switching activity. The designed flip-flop shows improved propagation delay compared to the TSPC flip-flop but consumes more power due to its complex structure and higher transistor count. This analysis provides a deep understanding of the effect of transistor configurations and parasitic elements on the performance of D flip-flops.