Publication: Pmon feature validation in pre-silicon ip validation
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Date
2024-07
Authors
Wang, Li Ren
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Abstract
The project, "PMON Feature Validation in Pre-Silicon IP Validation," was initiated to address the growing need for comprehensive validation techniques in the
field of semiconductor development. With advancements in technology, there arose a demand for thorough investigation and validation of Performance Monitor features to ensure the reliability and performance of semiconductor chips. The primary objectives of the project were to conduct a detailed study of Performance Monitor concepts and theories and to analyze the architecture and design of Performance Monitor structures. Using advanced tools such as Synopsys Verdi, PyCharm, and DVT Eclipse IDE, the project sought to formulate pre-silicon validation procedures dedicated to Performance Monitor features, optimizing precision and dependability. The methodology involved a systematic approach encompassing stimulus, checker, and coverage stages, focusing on reviewing past validation attributes, updating these attributes to align with evolving semiconductor design standards, and enhancing checker functionality. Through implementation, key findings of the project emerged such as an increment in the efficiency and accuracy of the Performance Monitor, proven by the significant achievement of pushing the checker coverage percentage from 52.38% to 84.21%. The project's outcomes contribute to the ongoing advancement of semiconductor design and validation practices, ensuring the reliability and performance of future semiconductor chips.