Publication: Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology
| dc.contributor.author | Ong, Ern Seang | |
| dc.date.accessioned | 2024-09-10T02:57:50Z | |
| dc.date.available | 2024-09-10T02:57:50Z | |
| dc.date.issued | 2013-02 | |
| dc.description.abstract | Through-silicon via (TSV) technology has been an emerging technology to 3D heterogeneous system integration through vertical interconnection. This promising technology enables smaller footprints, reduced signal delay, shorter interconnections, lower power consumption and higher integration density as compared to the existing 2D planar system integration and 3D IC with wire bonds. Despite all the benefits, there are still many challenges ahead for this technology to be both technically and economically viable. Plastic encapsulation process is one of the critical challenges in the continual shrinking of TSV diameter, wafer thickness and microbump pitch. In this thesis, both experimental and numerical approaches are used to study the plastic encapsulation process in 3D IC package with TSV. The objectives of this research include establishing feasible methods to analyze flow front advancement, pressure distribution, velocity profile and curing rate of epoxy molding compound during encapsulation process. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/20406 | |
| dc.subject | Analysis Of Plastic Encapsulation Process In 3D | |
| dc.subject | Package With Through-Silicon | |
| dc.title | Analysis Of Plastic Encapsulation Process In 3D IC Package With Through-Silicon Via (Tsv) Technology | |
| dc.type | Resource Types::text::thesis::master thesis | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |