Publication: Performance analysis of operational amplifier circuit with miller compensation using CMOS 180nm technology
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Date
2024-08
Authors
Mohamad Anas Luqman bin Mohamad
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Abstract
In modern electronics, efficient and high-performance operational amplifiers are crucial, especially in applications like implantable medical devices. This project
aims to advance the field by developing a two-stage operational amplifier with Miller capacitor compensation using Cadence 180 nm technology. The primary goal is to design and analyze the performance of this amplifier to meet specific performance metrics. The objectives are to achieve an average power consumption of less than 300 µW at a 1.8V voltage supply and attain a CMRR exceeding 70 dB for the proposed operational amplifier circuit. These goals were successfully met, with the amplifier demonstrating a power consumption of 250.595 µW at a common-mode voltage (Vcm) of 1.6V and 220.01 µW at a Vcm of 0.8V. Additionally, the amplifier achieved a CMRR of 92.202 dB, significantly surpassing the initial target. CMOS technology offers advantages such as low power consumption and high integration capabilities, making it ideal for applications ranging from portable health monitors to sophisticated implantable devices. However, optimizing power efficiency while maintaining balanced performance remains a challenge. This project addresses these challenges by employing advanced compensation techniques in the design of the operational amplifier. By achieving the specified objectives, this study enhances the energy efficiency of CMOS operational amplifiers while maintaining high performance standards. The outcomes contribute to the development of operational amplifiers widely used in low-power devices.