Publication: New practical repeater and clock network design methodologies for complex system-on-chip (soc) using hybrid meta heuristic technique
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Date
2022-02-01
Authors
Teh, Eng Keong
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Abstract
With the advent of deep-submicron technology, the delay of interconnects, especially global signals and clock networks which connect the intellectual property (IP) blocks, have become the key performance limiting factors to a System-on-Chip (SoC). Furthermore, with significant increases in SoC design complexity, such as larger die size, more digital and analog mixed signals IPs, higher clock frequency, more clock domains, lower power consumption requirements, lower development cost, and shorter design schedule, global repeater and clock network design havebecome nondeterministic polynomial-time hardness (NP-Hard) problems that arecomputationally hard problems where the best algorithms known so far have exponential time complexity. As a result, most of the prior works are either no longer practical or not sufficient for the recent complex SoC. This thesis presents new
practical repeater and clock network design methodologies that deploy hybrid meta heuristic (HM) techniques. The proposed methodologies combine meta-heuristic algorithms with different artificial intelligence algorithms such as exact and heuristic algorithms, to make correct guesses for certain decisions and subsequently achieve near global optima results in shorter turn-around time. Specifically, this thesis proposed HM techniques which use a Genetic Algorithm (GA) based flow to find near optimum repeater recipe as well as a Mean-shift Algorithm based flow to optimize floorplan pin before correctly insert global buffer and flop repeaters into a complex SoC. Based on results from buffer repeater insertion experiments on a 14 nm SoC, it showed that the proposed techniques did further improve 43% of total timing path and reduce 9.09% of total power consumption with 83.33% less design convergence turn-around-time. In terms of flop repeater insertion, the proposed techniques had successfully inserted 539k flop repeaters into a 10 nm SoC and saved approximately 30 men-month efforts. Other than global signals repeater insertion techniques, the thesis also introduces a flexible full chip (FC) clock network topology and a HM flow which utilizes a k-mean based synthesis algorithm to search for near optimum global clock distribution solution in shorter turn-around time. With these techniques, clock repeaters were inserted into two SoCs built in 10 nm and 7 nm technology nodes with averagely 16.98% better FC clock skew for 10 nm SoC and 28.89% for 7 nm SoC compares to a conventional ASIC technique. On top of skew improvement, the proposed technique had achieved 64.5% less turn-around-time in FC clock balancing phase of the 10 nm SoC. Based on the results, it was depicted that the practicality and effectiveness of the proposed hybrid meta-heuristic algorithm-based repeater insertion and clock distribution
methodologies in reducing design turn-around-time were proven. In conclusion, it is suggested that while industry computer aided design (CAD) tool vendors continue improving local optimisation heuristic algorithms, SoC designers are recommended to invest in hybrid meta-heuristic techniques, which combine the industry heuristic algorithms with meta-heuristic algorithms from academic knowledge pool and exact algorithms from subject matter experts, for the global optimisation.