Publication: Digital up converter
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Loh, Kok Khoon | |
| dc.date.accessioned | 2024-08-07T01:23:07Z | |
| dc.date.available | 2024-08-07T01:23:07Z | |
| dc.date.issued | 2008-05-01 | |
| dc.description.abstract | With the development of the 3G-wireless infrastructure, transmitter/receiver functionality has become a focus to designer. Digital Up Converter (DUC) sub-systems are among the main digital components of the transmitter functionality. An efficient low-cost DUC implementation that meets increasing data service is highly desired. DUC is an algorithm, used to filter and converter the digital baseband signal to a higher sampling rate before being modulated onto a direct digitally synthesized (DDS) carrier frequency. A possible DUC algorithm consists of Finite Input Response (FIR) filter, Cascading Integrating Comb (CIC) filters, mixer and DDS. This project is applied for WCDMA application. Implementation of the DUC algorithm using the Xilinx System Generator has been made for Xilinx Virtex-4 Field Programmable Gate Array (FPGA). Xilinx Virtex-4 FPGA board is the best solution due to its smaller technology size, flexibility and energy consumption. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/20068 | |
| dc.language.iso | en | |
| dc.title | Digital up converter | |
| dc.type | Resource Types::text::report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |