Publication: Building a clock for analog to digital converter timing test
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Date
2010-04-01
Authors
Heng, Yeh En
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Abstract
This thesis presents the building of a low-cost, high precision clock for the ADC timing test. There are sixteen clock stimuli required to drive the ADC chip. The 40-pin device-under-test (DUT) ADC is having a resolution as high as 12-bit. The frequency of the designed clock is 2 MHz and the voltage level is 3.3V. The proposed approach utilizes the use of simple digital logic gates to perform all the sixteen clock generation. In short, the circuit is divided into three parts; constant frequency ring oscillator, duty cycle adjustment circuit and voltage regulation circuit. Extra care is emphasized in selecting the most appropriate logic gates for circuit as different family and manufacturer of the gates leads to different results. In the proposed methodology, the model is built on a printed circuit board for a more stable performance. The test methodology was verified in simulation using MULTISIM as well as in hardware. Results show that the proposed methods in generating clocks are easy and accurate. The concept involved in the whole circuit is not complicated and easy to be comprehended. Besides, a 6-bit digital counter is constructed as the supplementary circuitry to test the digital-to-analog converter (DAC). The DAC is meant to translate back the digital output from the ADC to the analog output. Comparison between the DAC analog output and the original analog input is essential to verify the performance of the ADC. As a conclusion, the proposed clock design is the best options compared to others.