Publication: CMOS 65nm low noise 62.6µw operational amplifier design
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Ameerah Adlina binti Azhar | |
| dc.date.accessioned | 2025-02-17T08:36:42Z | |
| dc.date.available | 2025-02-17T08:36:42Z | |
| dc.date.issued | 2023-08 | |
| dc.description.abstract | In the new phase of industrialization, where humans collaborate with advanced technologies such as robots and machines, the significance of sensors in the industry has increased. There is a growing demand for high-precision amplification in sensory systems to handle analog signals. However, achieving high precision amplification in CMOS amplifiers is challenging, primarily due to limitations imposed by flicker noise, especially at low frequencies. Despite the demand for high precision amplification, CMOS amplifiers with high sensitivity face challenges in mitigating flicker noise, particularly in the low-frequency range. This project proposed a lownoise low-power operational using gm increment technique to reduce flicker noise at the input. The proposed amplifier utilizes a differential amplifier with current mirror load to amplify the input signal. The amplifier was designed in 65nm CMOS technology achieving 28dB gain and 90° phase margin. The input-referred noise of the operational amplifier at 15Hz was 1.027µV/√Hz and consume 62.6µW power consumption at 1.2V supply. The design gain bandwidth is 6.632MHz. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/21086 | |
| dc.language.iso | en | |
| dc.title | CMOS 65nm low noise 62.6µw operational amplifier design | |
| dc.type | Resource Types::text::report::technical report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |