Publication: Block-level verification of block random access memory (BRAM) in FPGA
Loading...
Date
2024-08
Authors
Yeoh, Wei Loon
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
This project presents a study on block-level verification of Block Random Access Memory (BRAM) in Field-Programmable Gate Arrays (FPGAs). The
motivation behind this study arises from BRAM's significant role in current FPGA based systems, where memory performance and reliability are crucial. If only using simulation-based verification, it had limits in large and complex designs due to longer simulation times, limited problem detection ability, and complex debugging processes. Hence, the verification implemented in this project is assertion-based verification. The methods used include creating and running an extensive and diverse set of verification testcases and implementing assertions for all outputs in the verification environment. The outline of the testcases developed is explained and detailed in the testplan. All the testcase and testbench code, including the assertions, are created and developed in Vivado software. After running the simulation, all the testcases are obtained 100% assertion coverage, meaning all the testcases are passed. Since all the testcases get passed, the test pass rate calculated is also 100%. This indicates that the BRAM design operates correctly under the specified conditions. The results demonstrated that the proposed verification technique works effectively at obtaining a 100% test pass rate and assertion coverage, verifying the functionality and correctness of the BRAM design. Therefore, the BRAM design performs correctly as follows the specification document.