Publication: Duty cycle correction circuit using 50nm CMOS process
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Date
2023-07
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Abstract
In high speed digital circuitry, duty cycle correction circuit has been used extensively. Due to the Double Data Rate (DDR) system's rapid development, a more
demanding clock with a 50% duty cycle is needed. This clock must have a wide input correction range, higher accuracy, and wide operating frequency. This project proposes a duty cycle correction circuit which operates at frequency between 1GHz to 3GHz. The proposed circuit functions to precisely correct the input waveforms’ duty cycle to 50%. In order to achieve the desired duty cycle correction, the circuit uses a combination of differential pair transistors, biasing components and feedback mechanisms. The circuit works by comparing the input waveform to a reference voltage. The circuit corrects the input waveforms’ pulse width to achieve the desired duty cycle by adjusting the biasing conditions and utilizing the feedback techniques. Simulations are performed using LTspice software to verify the functionality and performance of the proposed duty cycle correction circuit. In order to meet the design requirements, some parameters such as Vbias, resistance, capacitance and transistor sizes are optimized.