Publication: Design of 2.14ghz low power consumption low noise amplifier for w-cdma applications using 0.18-μm cmos technology
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Lim, Mei Ching | |
| dc.date.accessioned | 2024-08-14T01:44:49Z | |
| dc.date.available | 2024-08-14T01:44:49Z | |
| dc.date.issued | 2007-03-01 | |
| dc.description.abstract | Due to the growing demand on wireless transceivers, Integrated Circuit (IC) technology is required to be able to integrate both RF and base-band functions onto a single chip for low power and low cost transceivers. The first stage of a receiver is typically a low noise amplifier (LNA), whose main function is to provide enough gain to overcome the noise of subsequent stages (such as mixer). Aside from providing this gain while adding as little noise as possible, the LNA should accommodate large signals without distortion. It must also present specific impedance, such as 50 Ω, to the input source. In this work, CMOS cascode Low Noise Amplifier (LNA) with Current Reuse Technique and inductive source degeneration structure which not only able to meet the requirements of typical W-CDMA performance but also consumed low power was designed and analyzed. Current Reuse Technique was employed to reduce power consumption and achieve the same amplifier transconductance to enable the LNA to achieve good gain. The proposed Current Reuse Technique required a supply voltage of 1.8 V with only 2.95 mA current drawn and hence dissipates 5.31 mW. Apart from that, the designed LNA achieved noise figure of 2.15 dB with gain of 16.05 dB. The Input Third-order Intercept Point, IIP3 and Input 1-dB Compression Point, P-1dB of the designed LNA are -13.82 dBm and -23.70 dBm respectively. Besides these, S11 and S22 are -19.9 dB and -29.23 dB respectively while reverse isolation (S12) is -52.47 dB in a 50 Ω environment. The whole project stages comprise design, simulation, analysis, design rules check (DRC) and layout versus schematic (LVS). All the LNA performances are checked through Cadence Spectre by using Silterra 0.18 μm technology process. Detailed analysis about theories and analysis of LNA had been dicussed thoroughly in this project. The layout area (including the bonding pads) is approximately 1.27x0.8 mm 2. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/20259 | |
| dc.language.iso | en | |
| dc.title | Design of 2.14ghz low power consumption low noise amplifier for w-cdma applications using 0.18-μm cmos technology | |
| dc.type | Resource Types::text::report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |