Publication: Developing a high-speed ripple carry adder with fault detection and localization
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Quak, Ting Sheng | |
| dc.date.accessioned | 2025-03-28T03:47:12Z | |
| dc.date.available | 2025-03-28T03:47:12Z | |
| dc.date.issued | 2023-08 | |
| dc.description.abstract | Adder is the most important unit in ALU as addition is used in many operations. Ripple-carry adder (RCA) is one of the most common types of adders. However, its low speed limits the application. In this thesis, a high-speed parallel RCA (PRCA) along with fault detection and localization is designed, by combining the salient features of Carry Select Adder (CSA) and carry look-ahead adder (CLA). Besides, the first carry-in bit for each block is generated by a carry look-ahead logic (CLL) to reduce the propagated delay. The proposed design is divided into blocks and the schematic design of each block is constructed by using Quartus II. The design module is created by using Synopsys tools and written in Verilog language. The compilation and synthesis of logic design is done on Design Compiler (DC). The results can be observed from the reports generated by the tool. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/21416 | |
| dc.language.iso | en | |
| dc.title | Developing a high-speed ripple carry adder with fault detection and localization | |
| dc.type | Resource Types::text::report::technical report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |