Publication: Design an aes encryption ip core using the aes rijndael block cipher algorithm
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Date
2024-07
Authors
Eunice, Fong Phaik Yin
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Abstract
This thesis aims to design an AES Encryption IP Core using the AES Rijndael Block Cipher Algorithm in Verilog for AES-256 bit encryption, with a focus on integrating Cipher Block Chaining (CBC) mode for enhanced security. Implementing AES-256 bit encryption in hardware offers secure data transmission and storage, making it ideal for high-security applications. However, the current implementation lacks CBC mode, which is key for ensuring secure and reliable encryption. Integrating CBC mode enhances the security of the AES encryption IP core by introducing an extra layer of security through a feedback mechanism, making it more resilient against certain types of attacks. The process involved in this design includes KeyExpansion, SubByte, ShiftRows, MixColumns, Add_Round_Key and CBC. The Verilog implementation of the AES Encryption IP Core will be thoroughly tested to ensure correct operation and adherence to the AES standard. The final design will be synthesized and implemented on an FPGA board to demonstrate its practicality and effectiveness. However, due to
the limitation of number of pins available in the device used, the cipher key will be loaded into the system using the Serial Peripheral Interface (SPI) method. By using SPI, the process of loading the cipher key into the AES encryption system is simplified both in terms of hardware and software, reducing development complexity and time (5 clock cycles). Lastly, the AES encryption design results will be compared with those from an online decryption calculator to ensure the expected outcomes are achieved.