Publication: Preliminary noise study of low noise amplifier for 0.13 mm and 0.18 mm cmos process technologies
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Date
2010-03-01
Authors
Koh, Hee Lee
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Abstract
A detailed and systematic noise study of the inductively-degenerated cascode LNA, which is also known as the Simultaneously Noise and Input Matching (SNIM) LNA is presented in this
thesis. The architecture of SNIM LNA is first studied. This is followed by studies on the standard and extended MOSFET noise models, where noise contribution of the cascode(common-gate)
transistor is taken into consideration. Next, the extended MOSFET noise model is used to develop the power-constrained noise optimization (PCNO) technique for the selection of optimum
device width. Noise figure contours are constructed as a graphical means to understand the relationship of design parameters (r, Qs, and PD) and to estimate the noise figure of the LNA. Three
LNAs are designed using power-constrained simultaneous noise and input matching (PCSNIM) design methodology. Two of these PCSNIM LNAs have the operating frequency of 2.4 GHz,
supply voltage of 1.8 V, and is realized using Silterra’s 0.18 mm process technology. The third PCSNIM LNA is designed using Silterra’s 0.13 mm process technology with 1.2 V supply voltage
and 2.4 GHz operating frequency. All there LNAs have buffer for 50 W output matching, two of which(0.18 mm and 0.13 mm) with common-drain buffer and the other with class AB buffer (0.18
mm). Subsequently, experimental results are obtained through simulation. The performance metrics of interest include the scattering parameters, noise figure, linearity (IP1dB and IIP3), and DC
response. Noise figure breakdown for the LNA is performed to identify noise contribution for each component. Comparison on noise figures obtained from calculation and simulation is then made. It was found that the noise figure contour and NF expression based on the standard noise model yield satisfactory result when compared to the simulation result.