Publication: Design of 8 bits parallel to-serial converter for baseband using vhdl
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering | |
| dc.contributor.author | Abdullah Zawawi, Ruhaifi | |
| dc.date.accessioned | 2024-05-29T09:35:01Z | |
| dc.date.available | 2024-05-29T09:35:01Z | |
| dc.date.issued | 2006-05-01 | |
| dc.description.abstract | This report included code writing, schematic, layout and simulation result for front end and backend process. This design is actually done for digital signal processing and still need more effort in research since this project is still new in our university. Front end process consists of behavioral description, RTL description and gate level description. Synthesis is done throughout this process to specify the maximum frequency for clock signal. This design has achieved frequency of 204MHz at typical process with 162238.88um2 in total area and only 0.0294mW in power consumption. Our target is to get high speed system to produce high data rate. We also want to reduce the power consumption especially the dynamic and static power. For front end, the design had been carried out for behavioral description, synthesis and verilog in for gate level simulation. Then, the gate level netlist will be imported for back end process included its timing constrain. A simple floorplan is generated, blocks or cells are placed, power routing is done and all analysis for timing, violation ,clock tree and fixing all problems in our layout . Our target is to get GDSII file with no violation in setup and hold time, also no signal integrity problems. For back end analysis, there are no violation since the slack minimum slack value is 6.553ns for rising edge signal and 7.739ns for falling edge signal. The last process is very important because the parasitic resistor and capacitance have been considered so that the timing and power analysis will be more accurate. In addition, clock tree synthesis is carried out to arrange all standard cells at certain place in the core so that the clock signal will arrive at same time for all cells. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/19368 | |
| dc.language.iso | en | |
| dc.title | Design of 8 bits parallel to-serial converter for baseband using vhdl | |
| dc.type | Resource Types::text::report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |