Publication: Preliminary phase noise studies of Quadrature voltage control oscillator for 0.13mm cmos technology
Loading...
Date
2010-04-01
Authors
Ng, Kean Giap
Journal Title
Journal ISSN
Volume Title
Publisher
Abstract
Toward the second decade of the 21st century, wireless communication technology and radio frequency circuit is keep developing. The aggressive progress in down-scaling of the technologies
has caused the RF design to be more and more challenging, especially frequency synthesizer. This work will present the theoretical approach of phase noise on a 0.13 mm deepsubmicron
CMOS process technology LP3-QVCO. This 8-metals, 1-poly, 1.2 V LP3-QVCO has a 5 GHz center frequency. This design improve output performance utilizing 40W source damping
resistor (Rdamp), 200W tail biasing resistor (Rtail ) and 50W impedance common drain output buffers. The tank circuit consists of an on-chip spiral indctor and a CMOS varactor. The spiral
inductor is designed using "Analysis and Simulation of Spiral Inductance and Transformers" (ASITIC). The inductor has a quality factor of 18.6 at the center frequency. The CMOS varactor
is a multifinger gate width PMOS varactor (3.125 mm 64 = 200 mm) and it is tunable from 0.2 V to 1.2 V. The theoretical approach is carried out using Leeson model. Based on the model, some
analytic calculations for each parameter will be presented step by step, especially the quality factor (Q), noise figure (F), and output carrier power (P). Then, simulation is performed to validate
the theoretical approach. Furthermore, measurement result will be compared as well.