Publication: High-speed frequency lock detector using master-slave d flip-flop design
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Date
2024-10
Authors
Teoh, Sheng Yang
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Abstract
This project focuses on the design and analysis of a high-speed frequency lock detector (FLD) incorporating a master-slave D flip-flop (MSDFF) design. The FLD outputs an active low signal to indicate when the frequencies of a reference signal and a feedback signal are within a specified range. The FLD leverages the MSDFF to sample the UP and DN pulses from a phase frequency detector (PFD) and to enhance the accuracy of the lock range. FLDs are frequently used in applications requiring lock detection signals, such as GPS tracking loops. They can be constructed using various methods, including master-slave D flip-flops,
counters to count frequency, and capacitors to determine lock status. Six distinct MSDFF designs were developed and evaluated based on timing characteristics and power consumption. Of these, four were functional within the FLD framework. The performance analysis of the FLD involved signal verification to ensure output signal validity, as well as measurement of rise and fall times to identify the most effective FLD design. Additionally, VT corner analysis was conducted to determine the operational stability of each FLD under varying temperatures and voltage supplies. Among the MSDFF designs, MSDFF_V1 emerged as the most suitable for the FLD application. It demonstrated a delay of 187.7405ps, which is well within the 200ps threshold, and achieved rise and fall times of 56.13ps and 62.296ps respectively, both under the 70ps limit. Furthermore, MSDFF_V1 exhibited a power consumption of 39.95µW, significantly lower than the 100µW limit. The FLD_V1, constructed using MSDFF_V1, showed optimal performance across various temperatures and voltage variations from 1.6V to 2.0V, confirming its robustness. The MSDFF_V1 design meets the project's objectives by offering superior timing performance and low power consumption, ensuring the FLD operates efficiently and reliably under diverse conditions. This makes MSDFF_V1 the best candidate for high-speed frequency lock detection applications.