Publication: Design a 2.7ghz phase-locked loop (pll) in cmos 0.18µm technology
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Wong, Soon Yee | |
| dc.date.accessioned | 2024-08-12T01:39:52Z | |
| dc.date.available | 2024-08-12T01:39:52Z | |
| dc.date.issued | 2008-05-01 | |
| dc.description.abstract | Phase-locked loop (PLL) is an important element in communications, control systems, and instrumentation systems. In this project, the design of a 2.7GHz analog phase-locked loop is consisting of a phase detector (PD), charge-pump, loop filter, and voltage-controlled oscillator (VCO) is described. Topology of phase detector used is four-quadrant analog multiplier or Gilbert Cell multiplier, while second order passive loop filter is used for loop filter, and three stage ring oscillator as the VCO. Total number of transistors used for complete phase-locked loop is 16 transistors and total power consumption is 1.62mW. All the phase-locked loop simulation are using model library from SILTERA 0.18 CMOS technology with 1.8V supply voltage. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/20207 | |
| dc.language.iso | en | |
| dc.title | Design a 2.7ghz phase-locked loop (pll) in cmos 0.18µm technology | |
| dc.type | Resource Types::text::report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |