Publication: High efficiency carry save adder using modified-gate diffusion input (MOD-GDI) technique
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Date
2023-08
Authors
Teoh, Yong Keong
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Abstract
Adder is a fundamental and indispensable circuit for arithmetic operations in digital system where the performance of an adder is a significant factor. Hence,
design a high speed with small propagation delay, optimize the power consumption of a circuit to be more efficient and at the same time make the silicon area smaller are the goal of chip design in order to implement a greater number of adder into a digital circuit with good performances in terms of delay and power consumption simultaneously. To overcome the problem of optimization in term of power, performance and area (PPA) of integrated circuit (IC), Boolean simplification method and Modified-Gate Diffusion Input (MOD-GDI) are being implemented in designing the CMOS Full Adder cells. The designed cells are used to form a 4-bit Carry Save Adder (CSA) and undergo a comprehensive analysis by comparing with the basic CSA configuration in order to verify the method and technique that implemented in this research is able to optimize the power, performance and area. All simulations are performed through Cadence Virtuoso® based on SilTerra 180 nm technology process and generally the techniques implemented will result in reducing delay, lower the power consumption and area consumption as the number of transistor is reduce significantly. The techniques implemented throughout this research is appropriate for designing a 4-bit CSA while achieving the optimization in power, performance and area, and the most optimize design is the MOD-GDI 4-bit CSA with 500 ps propagation delay, with 3492.4688 µm2 of area consumption while average consuming 0.0031 mW of power.