Publication: Implementation of image processing technique in fpga
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering | |
| dc.contributor.author | Ng, Soo Kheng | |
| dc.date.accessioned | 2024-06-10T09:42:28Z | |
| dc.date.available | 2024-06-10T09:42:28Z | |
| dc.date.issued | 2006-05-01 | |
| dc.description.abstract | Traditionally, digital signal processing algorithms are implemented using software because of the complexities involved in the operations. In high-demand applications, application-specific integrated circuits (ASICs) are used. Faster processing usually comes at higher cost. With new, low cost and powerful FPGAs, hardware based digital processing can become affordable. The powerful processing system can cater to critical application such as in medical imaging for malaria parasite detection. Images can be processed in real time and this would be a great tool for medical practitioners. This project implements a 3X3 median filter system for the removal of noise from blood smear images for malaria parasite detection. The system is described using VHDL into three building blocks. Each block is state machine controlled and operates simultaneously. Two of the blocks are built based on modified standard architectures. Upon completing the software simulations, the hardware is built and the results show that the system is able to perform median filter to medical images. This system is able to process any medical images up to a preset size and have short processing time. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/19423 | |
| dc.language.iso | en | |
| dc.title | Implementation of image processing technique in fpga | |
| dc.type | Resource Types::text::report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |