Publication: Design of an 8-bit successive approximation register analog-to-digital converter
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Date
2008-05-01
Authors
Yap, Jee Jean
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Abstract
The market of semiconductor field is dominated with different kinds of electronic devices such as microprocessor, video-audio applications, wireless communication, etc. The increasing demand for mixed-signal design makes design of an effective mixed-signal device becomes competitive. Analog-to-digital converters (ADCs) are widely used in mixed-signal circuits; therefore designing a good ADC is critical. Due to impressive improvement of technology today, a comparative ADC needs to have high sampling rate, high resolution and low-power consumption. This thesis presents the transistor-level implementation and simulation of a 8-bit successive approximation register (SAR) ADC schematic in 0.18µm Silterra CMOS technology. Overall block diagram and principle of the SAR ADC is studied. Chapter 3 shows the implementation of the SAR ADC schematic using Cadence Virtuoso software. A bottom-up methodology is used, where the blocks are implemented and simulated individually before integrating into an SAR ADC. The SAR ADC contains four major blocks: open-loop two-stage comparator, SAR control logic, sample and hold circuit with clock booster and R-2R ladder digital-to-analog converter. The functionality and performance of the ADC is investigated. ADC parameters such as accuracy, resolution, integral non-linearity, differential non-linearity and sampling rate are measured. The outcome for the simulations shows room for improvement. However, the behavior of the SAR ADC is verified. The sampling-rate of the ADC meets the requirement, but the accuracy of the SAR ADC fails to fulfill the requirement due to offset error and gain error of the device. Within the limitations of the research, the transistor-level circuit design of an SAR ADC is found to be successfully integrated and tested.