Publication: Power and area estimation of router in network on chip (NOC) using machine learning
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Date
2023-08
Authors
Chin, Hong Kai
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Abstract
NoCs have become an increasingly popular solution for on-chip communication in modern System-on-Chip (SoC) designs. It has replaced bus system for communication as it is more systematic and faster compared to old architecture. However, the power consumption of the router in NoC is always a problem as high-power consumption will reduce the efficiency of NoC. Traditional methods such as time-consuming methods for estimating the power consumptions and area of the routers are inefficient. Hence, this paper proposes a machine learning-based approach for estimating the power consumption and area of a router in a
Network on Chip (NoC). Accurate estimation of the power and area of the router is crucial for optimizing the overall performance and cost of the NoC. The proposed approach uses a combination of machine learning models, including linear regression and neural networks, trained on a set of simulation data to predict the power and area of the router. The accuracy of the model is test using test set. Moreover, unseen data is used to test the performance of the model under unfamiliar environment. To further verify the robustness of the model, k-fold cross-validation is used. R-Squared performance metric is used as it is easy to interpret. The aim is to make sure all the regression models can achieve at least 0.70 score. The regression models with the best hyperparameter are compared and selected. Random forest regression model score 0.9968 and 0.9967 by test set, 0.9960 and 0.9949 under unfamiliar environment and mean scores of 0.93 under cross validation when estimating the area and power of router. The result show that random forest regression model with number of tree equal to 200 has the best fit to the data for estimating the power and area of the router.