Publication: FYP 2024_ 5.8 GHz silicon substrate bandpass filter
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Date
2024-08
Authors
Flora, Chang Hen Ying
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Abstract
This project aimed to design, optimise, and fabricate a 5.8 GHz bandpass filter implemented on a silicon wafer substrate with dielectric constant of 11.9. The
development of specialized filters tailored for specific frequencies is crucial due to the increasing demand for wireless communication systems such as Internet of Things (IoT), radar system, satellite, and Wi-Fi applications. The bandpass filter was designed with the concept of microstrip transmission line and hairpin configuration which aimed to address the requirements by providing a suitable passband in the frequency range of 5.3 GHz to 6.3 GHz and centered around frequency of 5.8 GHz. The design process involved some RF design principles, utilizing the properties of silicon wafer as a substrate, and employing CST Studio Suite as design and simulation tool to validate and optimize the design. During the simulation, some important parameters such as return loss, insertion loss and bandwidth were observed to ensure that the bandpass filter met the desired specifications. After the simulation, the optimisation process was done repeatedly to enhance the filter performance. Before the silicon substrate bandpass filter was fabricated, the bandpass filter with Roger RO4003C substrate was designed and
fabricated to verify the design. It was then used as reference to design silicon substrate bandpass filter. The silicon substrate bandpass filter was successfully designed with area dimension 19.99 mm x 6.10 mm, fractional bandwidth (FBW) of 17.73%, insertion loss of 1.15 dB and return loss of 17 dB (Port 1) and 68.58 dB (Port 2). However, the fabricated silicon substrate bandpass filters failed to perform efficiently and properly due to some technical issues which have been discussed.