Publication: Drrii sdram stressing and validation algorithm (intel)
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering | |
| dc.contributor.author | Chuah, Siang Chun | |
| dc.date.accessioned | 2024-10-02T03:45:31Z | |
| dc.date.available | 2024-10-02T03:45:31Z | |
| dc.date.issued | 2009-04-01 | |
| dc.description.abstract | DDRII DRAM functions as the computer’s memory in a computersystem. It is used to store information in binary which is 0’s and 1’s. The speed of the memory has increased rapidly because of the fast technology development. In order to verify the memory is compatible or able to use in the system, a test called as MSTRESS has been developed. The program is designed to stress and validate the memory to make sure the memory is working in the right timing and do not give invalid or wrong data. Unfortunately, the algorithm and the flow of the program are not recorded. A study through the program source code is needed to understand the algorithm. To understand the algorithm of the program, the fundamental knowledge of memory and cache has to be studied. Then, reverse engineering through the source code of the program will be done. Other than that, tests are carried out to validate the program. Through the careful studies and test, it shows that the algorithm of program is capable to stress and validate the memory in a computer system. The algorithm is able to ensure that the data mismatched do not happen and the timing of the memory is compatible to the system. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/20640 | |
| dc.language.iso | en | |
| dc.title | Drrii sdram stressing and validation algorithm (intel) | |
| dc.type | Resource Types::text::report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |