Publication: Circuit development and layout implementation of benchmark circuit in 180nm CMOS technology
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Joel Matthew a/l Thomas Matthew | |
| dc.date.accessioned | 2025-05-15T08:13:13Z | |
| dc.date.available | 2025-05-15T08:13:13Z | |
| dc.date.issued | 2024-08 | |
| dc.description.abstract | Power consumption and delay are the two most crucial aspects of circuit development and layout implementation, and it is challenging to optimize all aspects at once. This research is designed to help overcome this challenge by examining power consumption and delay effects in digital circuits operation at an ideal voltage of 1.6V. Additionally, this research is also conducted to help develop the first layout implementation of the benchmark circuit with area reduction of 10%. By using new layout techniques accompanied by simulations, the layout plans were able to prove the influence of different layouts on the signal passed through circuits, which is why efficient layouts must be employed. Finally, through the properties of layout design and the research conclusions, it has offered great suggestions for higher functionality and sustainable electrical devices. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/21652 | |
| dc.language.iso | en | |
| dc.title | Circuit development and layout implementation of benchmark circuit in 180nm CMOS technology | |
| dc.type | Resource Types::text::report::technical report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |