Publication: Power grid design for optimum ir-drop
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Ng, Wei Zhang | |
| dc.date.accessioned | 2025-05-30T02:18:36Z | |
| dc.date.available | 2025-05-30T02:18:36Z | |
| dc.date.issued | 2024-07 | |
| dc.description.abstract | This project addresses key issues in power grid design to optimize IR-drop, driven by the need for efficient power delivery in high-performance electronic systems. The research identifies challenges and provides recommendations for minimizing IR-drop. The methodology involves creating a schematic with Cadence Virtuoso, developing a detailed layout floorplan, completing pin placement and routing, and applying power grid techniques to mitigate IR-drop. Physical verification through DRC and LVS checks ensures design compliance, followed by post-layout simulation to evaluate IR-drop. If necessary, alternative power grid techniques are implemented to meet specifications. The project emphasizes the importance of component placement, routing techniques, and decoupling capacitor selection. The findings offer insights and best practices for both academic research and industry applications in enhancing power grid performance and electronic system design. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/22015 | |
| dc.language.iso | en | |
| dc.title | Power grid design for optimum ir-drop | |
| dc.type | Resource Types::text::report::technical report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |