Publication: Improved ripple carry adder with reduced delay and low power consumption at circuit level using 180 nm technology
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Date
2023-08
Authors
Ong, Shi Mei
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Abstract
Full adder serves as the functional building block and basic element in numerous designs used in very-large-scale integration (VLSI) and digital signal
processing (DSP) applications. Adder is a versatile component for addition, multiplication, arithmetic logic unit construction, etc. Its importance necessitates the
development of an efficient adder block. To achieve high speed and low power consumption, various approaches can be employed. In this work, 4-bit Ripple Carry Adder (RCA) at circuit-level using conventional, Boolean simplification, Boolean simplification with transistor sizing and modified Gate Diffusion Input (m-GDI) logic is presented using Cadence Virtuoso® software based on Silterra 180 nm technology. The comparison and analysis of several approaches to reducing the latency and power consumption of 4-bit RCA circuits is the main emphasis of this study. Performance factors such as delay and power consumption are evaluated based on four different 1 bit Full Adders (FA), which are Basic FA (FA_1), Boolean simplified FA (FA_2), Boolean simplified with Transistor Sizing FA (FA_3), and m-GDI FA (FA_4). The design of the four 1-bit FAs is then incorporated into a 4-bit RCA, and the impact on large-scale design is contrasted and examined. The results showed that the m-GDI based 4-bit RCA (4bit_FA_4), which uses 32 transistors, demonstrates the most optimized performance in terms of power consumption and propagation delay, with values of 285.4 nW and 118.845 ps, respectively.