Publication: A square wave clock generator using ring oscillator in CMOS 180nm technology
| datacite.subject.fos | oecd::Engineering and technology::Electrical engineering, Electronic engineering, Information engineering::Electrical and electronic engineering | |
| dc.contributor.author | Devika | |
| dc.date.accessioned | 2025-05-15T03:50:12Z | |
| dc.date.available | 2025-05-15T03:50:12Z | |
| dc.date.issued | 2024-07 | |
| dc.description.abstract | This project aims to design and implement a square wave clock generator using a ring oscillator in CMOS technology with a 180 nm process. Clock generators are essential for providing timing signals in digital systems. The 180 nm CMOS technology is chosen for its low power consumption, high noise immunity, and suitability for integrating many transistors on a single chip, reducing overall footprint and power usage. The ring oscillator, consisting of an odd number of inverters in a loop, produces a square wave output by oscillating between high and low states. This simple design is ideal for CMOS technology, offering a balance between performance, power consumption, and manufacturing cost. The design process involves optimizing parameters to achieve a stable and accurate square wave output. Transistor sizing is crucial, as it impacts oscillation frequency and power consumption. Smaller transistors switch faster but may leak more current, while larger ones consume more power but offer better stability. Biasing ensures proper transistor operation, and layout optimization minimizes parasitic capacitances and resistances that can degrade performance. Techniques like dynamic voltage scaling, clock gating, and optimizing the supply voltage reduce power consumption. Ensuring signal integrity involves reducing jitter and maintaining consistent frequency, which is critical for reliable digital system operation. Cadence EDA tools are used to validate the clock generator's performance, enabling simulation and analysis of frequency stability, jitter, and power consumption. Simulation results ensure the design meets advanced digital applications' stringent requirements. The successful implementation of this project will advance clock generation technologies for integrated circuits, specifically targeting the 180 nm CMOS process. | |
| dc.identifier.uri | https://erepo.usm.my/handle/123456789/21639 | |
| dc.language.iso | en | |
| dc.title | A square wave clock generator using ring oscillator in CMOS 180nm technology | |
| dc.type | Resource Types::text::report::technical report | |
| dspace.entity.type | Publication | |
| oairecerif.author.affiliation | Universiti Sains Malaysia |